Top Tech Jobs & Startup Jobs in Denver & Boulder, CO

17 Days AgoSaved
In-Office
Fort Collins, CO, USA
122K-195K Annually
Senior level
122K-195K Annually
Senior level
Software • Semiconductor • Manufacturing
Design and deliver high-performance flip-chip BGA ASIC packages addressing signal integrity, power integrity, thermal, reliability, and manufacturability. Perform physical layout, manage multiple projects, interface with customers and vendors, and improve design processes and automation.
Top Skills: Adc/DacAllegro Package DesignerCadence ApdCadence SkillDdr5Flip-Chip BgaHbmSerdes (224G+)
Reposted 17 Days AgoSaved
In-Office
Fort Collins, CO, USA
110K-176K Annually
Senior level
110K-176K Annually
Senior level
Software • Semiconductor • Manufacturing
Develop, characterize, and sustain photolithography processes for high-volume Si MEMS production. Own photo processes and tools, manage SPC/overlay, lead experiments and data analysis, troubleshoot yield/defect issues, and drive long-term process improvement with Equipment Engineering and cross-functional teams.
Top Skills: AccessAsml I-Line SteppersAsml Pas5500Chemically Amplified ResistsExcelFdcJmpMinitabPolyimide Thick ResistSpcSpotfireTel Act8TsvsWafer-Level Packaging (Wlp)
Reposted 17 Days AgoSaved
In-Office
Colorado Springs, CO, USA
88K-141K Annually
Senior level
88K-141K Annually
Senior level
Software • Semiconductor • Manufacturing
The U.S. Payroll Analyst manages payroll inputs, accounting, auditing, payment processing, and reconciliations, ensuring compliance with regulations and collaborating with HR and external providers.
Top Skills: Workday
Reposted 19 Days AgoSaved
In-Office
Fort Collins, CO, USA
60K-96K Annually
Entry level
60K-96K Annually
Entry level
Software • Semiconductor • Manufacturing
Design Engineer on Broadcom's Custom Silicon Design Team working on physical implementation of high-performance ASICs (3 nm and below). Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and signoff. Work in UNIX environments, use TCL (Python/Perl preferred) and commercial/in-house EDA tools, collaborate cross-functionally, and contribute to design flow automation and silicon bring-up. Requires Electrical/Electronics Engineering degree and strong VLSI/ASIC fundamentals.
Top Skills: 3 NmAsicCadence InnovusClock Tree SynthesisCmosDrcGdsiiLvsPerlPrimetimePythonRtlSocSynopsys Icc2TclUnix/LinuxVlsi
Reposted 19 Days AgoSaved
In-Office
Fort Collins, CO, USA
108K-173K Annually
Senior level
108K-173K Annually
Senior level
Software • Semiconductor • Manufacturing
Lead architecture and design of high-performance clocking solutions. Manage full lifecycle of analog timing IPs and validation, ensuring integration into SoCs.
Top Skills: ArcsimMatlab
Reposted 19 Days AgoSaved
In-Office
Fort Collins, CO, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Software • Semiconductor • Manufacturing
The Verification Engineer will develop verification plans, maintain UVM-based testbenches, analyze simulations, and collaborate with teams to ensure design quality.
Top Skills: AsicC/C++PythonRtlSystem VerilogUvm
24 Days AgoSaved
In-Office
Fort Collins, CO, USA
Senior level
Senior level
Software • Semiconductor • Manufacturing
Design and deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below), optimize PPA, perform CDC/RDC analysis and low-power techniques, drive timing closure and hand off to physical design, and collaborate with Architecture, Verification, and Physical Design teams.
Top Skills: 5Nm Process NodeClock Domain Crossing (Cdc) AnalysisDdrHbmHigh-Speed SerdesLow-Power Design TechniquesLpddrPhysical Design Hand-OffPpa OptimizationReset Domain Crossing (Rdc)Soc IntegrationSystemverilogTiming Closure
Reposted 25 Days AgoSaved
In-Office
Fort Collins, CO, USA
141K-226K Annually
Senior level
141K-226K Annually
Senior level
Software • Semiconductor • Manufacturing
The role involves designing flip-chip-BGA packages for ASICs, collaborating on designs, managing projects, and improving processes.
Top Skills: Allegro Package DesignerCadence ApdCadence SkillDesign Automation
Reposted 25 Days AgoSaved
In-Office
Fort Collins, CO, USA
108K-173K Annually
Senior level
108K-173K Annually
Senior level
Software • Semiconductor • Manufacturing
Design and optimize mechanical aspects of ASIC packages using FEA. Collaborate with teams, conduct validations, and document designs across multiple projects.
Top Skills: Ansys ClassicFeaMechanical
New

Track Smarter, Apply Better.

Ditch the spreadsheets. Organize your job search with our freeApplication Tracker.

Use For Free
Application Tracker Preview
All Filters
JobType
New Jobs
Job Category
Experience
Industry
Company Name
Company Size

Sign up now Access later

Create Free Account