Top Tech Jobs & Startup Jobs in Denver & Boulder, CO

Lead ownership and improvement of wafer-level test tool groups for MEMS/silicon devices. Specify, install, program, qualify and maintain probers/testers, ensure measurement accuracy and repeatability, drive continuous improvement projects, investigate yield and tool incidents, collaborate with cross-functional fab teams, and develop procedures, FMEAs, and monitoring (FDC/MES) for production and R&D.

Lead product lifecycle and go-to-market for Broadcom's PCIe switch portfolio. Define roadmap and ecosystem strategy for AI/ML server topologies, engage hyperscalers and OEMs, translate architecture requirements into hardware/software features, coordinate cross-functional teams, and drive pricing, enablement, and product P&L outcomes.

Own end-to-end QA for Brocade SAN products: design and execute functional, integration, regression, and performance tests; automate test cases and scripts; manage defects and report quality status; collaborate with developers, product managers, and stakeholders.

Develop and validate ATE test programs and flows for ASICs using Advantest/Teradyne platforms. Diagnose failures, create characterization tests, support qualification, analyze electrical/thermal root causes, perform volume data analysis, and collaborate with hardware and cross-functional teams on test methodology and extreme temperature testing.

Lead and manage external customer ASIC programs end-to-end, advise on EDA flows and best practices, perform physical design and STA checks, identify and mitigate design risks, coordinate cross-functional teams (test, packaging, fabrication, bring-up), and communicate technical findings to management and business teams.

Lead and manage customer ASIC programs end-to-end, advise on EDA flows and design best practices, execute physical design checks, assess and mitigate risks, collaborate with cross-functional teams, and support tape-out, bring-up, and production for advanced-node chips.

The Supply Chain Planning Analyst will support planning efforts, manage ERP issues, forecast production, and drive improvements in manufacturing processes at Broadcom.

Senior Digital VLSI Design Engineer responsible for defining and enforcing multi-clock synchronization, creating synthesis constraints, and driving full-chip CDC/RDC and DFT sign-off. Collaborate with architecture and chip leads to identify metastability and reset issues pre-RTL freeze, mentor teams, and implement automated sign-off flows for complex high-speed IPs.

Integrate and maintain commercial AI tools and LLM agents into VLSI design flows, coordinate multi-agent systems, optimize performance and QoR, deploy AI agents and chatbots, preprocess data, evaluate solutions, and train end-users to improve design productivity.

Design and deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below). Perform PPA optimization, CDC/RDC analysis, low-power design, timing closure, and hand off to physical design. Collaborate with Architecture, Verification, and Physical Design teams and drive SoC integration for high-speed memory and SerDes protocols.