Top Tech Jobs & Startup Jobs in Denver & Boulder, CO

Lead the DFT verification process for HBM, DDR, and SerDes designs, implementing methodologies, analyzing data, and ensuring design reliability through collaborative efforts with various teams.

The role involves supporting high-speed signal integrity design, simulation, modeling, and measurement analysis for high-speed digital applications.

The role involves developing timing constraints, performing static timing analysis, and ensuring timing closure for complex IP and ASIC blocks. Responsibilities include automating processes and guiding clock tree synthesis.

The Physical IC Design Engineer is responsible for executing physical design tasks including synthesis, verification, timing closure, place and route, and collaborating with RTL engineers. Requires experience from RTL to tape-out.

The DFT IC Design Engineer is responsible for implementing and verifying DFT aspects of silicon, collaborating with design engineers, and developing methodologies, requiring expertise in Siemens Tessent Tool and extensive experience in DFT design cycles.

The Physical IC Design Engineer will execute physical design tasks, oversee RTL to silicon tape-out processes, and collaborate with other engineers on design methodology.

The ATE Test Development Engineer will develop and validate test programs, assist with R&D and qualification testing, analyze root causes, and present findings. Requires advanced technical skills in test method development and debugging.

Responsible for developing and validating ATE test programs, analyzing test results, supporting R&D activities, and collaborating with cross-functional teams to improve test methodologies.

The Physical IC Design Engineer focuses on the execution of physical design, synthesis, verification, and timing closure while collaborating with RTL engineers and managing various design strategies.

The Analog/Mixed Signal Design Engineer will design, verify, document, and support complex IP for Enterprise Storage products, collaborating with various engineering teams.