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The Design Engineer will work on ASIC design, responsible for floor planning, routing, timing analysis, and physical integration of custom logic in high-speed ICs.

Design Engineer on Broadcom's Custom Silicon Design Team working on physical implementation of high-performance ASICs (3 nm and below). Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and signoff. Work in UNIX environments, use TCL (Python/Perl preferred) and commercial/in-house EDA tools, collaborate cross-functionally, and contribute to design flow automation and silicon bring-up. Requires Electrical/Electronics Engineering degree and strong VLSI/ASIC fundamentals.

Design and optimize analog blocks and systems, oversee layout, test performance, and collaborate with teams on IC products.

Oversee design and verification for SerDes development, including architecture design and RTL development. Emphasize timing analysis and constraints development.

The role involves defining chip-level floorplan architecture for ASICs, optimizing design for performance and area, and collaborating with cross-functional teams on integration.

Lead a cross-functional design team in developing HBM and die-to-die PHY IP, managing the architecture, design process, and project execution for high-quality ASIC products.

Responsible for managing a production team, ensuring safety and quality, and facilitating training and development. Involves communication with cross-functional groups and performance management of team members.

The role involves owning and optimizing plating equipment, troubleshooting, developing maintenance procedures, and collaborating on technological advancements in semiconductor processes.

The Solution Architect leads technical discovery for VMware Cloud Foundation, collaborates with clients and sales teams, and ensures solution adoption by architecting value-driven proposals and strategies.

Lead SoC DFT from specification through implementation and verification: insert and validate scan, BIST, TAP, and other DFT, generate and debug test vectors, support silicon bring-up and ATE diagnostics, collaborate with STA, physical design, customers, and manufacturing to meet test and yield goals.