Top Tech Jobs & Startup Jobs in Denver & Boulder, CO

Develops advanced 2.5D and 3D ASIC package solutions, balancing signal integrity, thermal performance, structural reliability, cost, and manufacturing requirements. Leads package technology development, qualification, supplier and customer engagement, sourcing, NPI, and production ramps. Collaborates with silicon, package design, test, marketing, and assembly teams while applying thermal and mechanical modeling and CAD tools to optimize substrates, interposers, materials, and assembly processes.

Develop and support software tools, methodologies, and automated flows for ASIC design and implementation. Responsibilities include scripting and C++ development, debugging design tools and flows, supporting IC designers, collaborating with EDA vendors, training global engineering teams, and documenting internal tools. The role requires digital logic and Verilog knowledge, software development expertise, static timing analysis, and power delivery verification experience.

Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G applications. Responsibilities include package layout, signal and power integrity, thermal and reliability considerations, manufacturability, and design of SerDes, ADC/DAC, DDR, and related structures. The engineer manages multiple projects, collaborates with global teams and vendors, interfaces with customers, and improves design processes through automation and documentation. This is a fully onsite role.

Design Engineer on Broadcom's Custom Silicon Design Team working on physical implementation of high-performance ASICs (3 nm and below). Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and signoff. Work in UNIX environments, use TCL (Python/Perl preferred) and commercial/in-house EDA tools, collaborate cross-functionally, and contribute to design flow automation and silicon bring-up. Requires Electrical/Electronics Engineering degree and strong VLSI/ASIC fundamentals.

Develops chip-level timing architecture, constraints, analysis, and signoff for advanced ASIC and SoC designs. Responsibilities include MMMC STA, pre- and post-route analysis, timing ECOs, violation debugging, signal integrity and clock analysis, timing-flow automation, and power/performance optimization. Collaborates with physical design, synthesis, and clock teams while contributing technical leadership, mentoring, methodology improvements, and timing documentation.

Executes the full physical IC design cycle from RTL through silicon tape-out, including synthesis, physical verification, timing closure, EM/IR analysis, place and route, clock tree synthesis, floorplanning, layout, and methodology development. Collaborates with RTL design engineers and applies TCL/Perl scripting and EDA tools. This is an in-person role in Colorado Springs, Colorado.

Lead DFT programs including specification, implementation, and verification for ASIC products, focusing on various phases of SoC DFT-related activities and customer interactions.

Designs complex front-end RTL IP blocks for leading-edge Ethernet switching silicon used in AI/ML and cloud data centers. Responsibilities include collaborating with global architecture and design teams, developing new device products, and emphasizing design and silicon debug. The role requires strong communication, documentation, self-direction, and teamwork, along with extensive industry experience in RTL design and familiarity with Python or Perl.

Architect, design, implement, and maintain low-level firmware, middleware, and diagnostic software for PHY chipsets. Develop and troubleshoot embedded C/C++ applications, collaborate with system and hardware designers, and provide leadership in architecture, design patterns, and code quality. Support the full development lifecycle, including pre-silicon co-simulation, laboratory hardware platforms, and silicon bring-up.

Designs and supports semiconductor timing solutions using static timing analysis, physical design principles, timing constraints, signal integrity, clock networks, and timing models. Debugs timing-tool errors, generates reports, analyzes setup and hold timing, and works with large datasets. Collaborates independently with geographically distributed engineering teams, manages multiple assignments, communicates findings clearly, and may supervise others. Requires extensive electrical or computer engineering experience and TCL programming.