Top Tech Jobs & Startup Jobs in Denver & Boulder, CO

Perform system-level signal and power integrity design, simulation, measurement and debug for high-speed SerDes systems (up to 400G). Collaborate with package, PCB, and silicon teams, develop EM and circuit models, perform VNA/TDR and oscilloscope measurements, correlate measurement-simulation, define SI/PI requirements, and support customer deliverables and documentation.

Lead technical project execution for 20+ concurrent package/PCB designs focusing on high-speed SerDes and high-power delivery. Manage and develop engineers, coordinate customers/vendors, create SI/PI methodologies, support package/PCB technologies, oversee lab measurements and correlations, and drive automation and project management practices.

Execute full-chip physical design from RTL to tape-out, including synthesis, place-and-route, timing closure (top-level STA), clock tree synthesis, EM/IR analysis, floorplanning, physical verification, flow/methodology development, and collaboration with RTL designers. On-site work required in Colorado Springs.

Design and deliver high-quality SystemVerilog RTL for advanced-node SoCs (5nm and below). Optimize PPA, perform CDC/RDC analysis and low-power design, drive timing closure and physical-design handoff, and collaborate with Architecture, Verification, and Physical Design teams. Work spans specification through tapeout readiness.

Perform full-chip physical IC design from RTL to tape-out including synthesis, place-and-route, STA/timing closure, EM/IR analysis, clock tree synthesis, floorplanning, and physical verification while collaborating with RTL designers and developing flows/methodologies.

Perform static timing analysis and timing closure for high-performance SoC ASICs. Work with logic and physical design teams to debug constraints, create timing ECOs, implement timing infrastructure, analyze critical timing paths, and develop scripts/methodologies. Document guidelines and communicate issues through to resolution.

Develop, validate, and optimize ATE test programs and flows for ASICs using Advantest/ExaScale/Teradyne platforms. Diagnose failures, perform electrical/thermal analysis, support qualification testing, collaborate with hardware teams, and analyze volume data to improve yield and screening.

Lead and develop an ASIC package design team creating complex flip-chip BGA packages for high-speed SerDes, HBM, DDR5 and RF applications. Manage 20+ concurrent projects, set technical methodologies and design rules, coordinate cross-functional and vendor collaboration, ensure SI/PI, thermal/mechanical integrity, drive automation and DFx tradeoffs, and support quoting and project tracking.

Verify Brocade Fabric OS and hardware switching platforms via manual and automated testing. Develop Python automation, create and execute functional/integration/regression/performance tests, track defects in JIRA, troubleshoot Linux/Windows/VMware and networking/SAN issues, and report quality status to stakeholders. Role is fully on-site.

Lead SoC architecture and IP integration for AI and storage chips. Drive design quality via simulation, synthesis, formal verification, and timing/physical optimization. Collaborate cross-functionally, consult layout/DFT, and produce SoC release collateral and specifications.