Lead architecture strategy for multi-die chiplet SoC platforms: define chiplet partitioning, D2D interconnect and QoS, power/clock/boot infrastructure, RAS/debug/telemetry, and system-level PPA/cost/yield trade studies. Drive cross-functional alignment and produce executive architecture recommendations for scalable data-center networking SoCs.

Lead end-to-end architecture of SoC compute complexes and high-performance memory subsystems for IPU/DPU platforms. Define CPU cluster designs, cache hierarchies, coherency models, DDR/HBM memory controllers, SMMU/IOMMU virtualization, and system-level integration with networking, storage, and accelerators. Optimize performance, power, scalability, and multi-generation roadmaps while collaborating across firmware, drivers, validation, and performance teams.