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Lead ASIC package architecture and detailed FC-BGA/MCM package designs for high-pin-count, high-speed, power-dense SoCs. Drive package trade studies (SI/PI, thermal, manufacturability, reliability), define standards, collaborate with silicon/RF/systems teams, work with OSATs and substrate vendors, and support qualification and production ramp.

Lead end-to-end RTL-to-GDSII physical design for high-performance SoCs in advanced FinFET nodes. Own synthesis, floorplanning, P&R, CTS, STA, DRC/LVS and sign-off; develop methodologies and automation to optimize PPA; drive timing closure, coordinate package/SI/PI and DFT, manage external PD partners and EDA tool flows, and support post-silicon bring-up and production for spaceflight-qualified designs.

Lead full physical design flow for complex SoC blocks and top-level integration from synthesis to GDSII. Drive timing closure, PPA optimization, physical sign-off (DRC/LVS, IR drop, EM), ECOs and tapeout. Collaborate with front-end, verification, DFT, packaging teams and external vendors, develop automation and methodology, and support products through production and spaceflight.

The role involves leading ASIC package design for FC-BGA and MCM solutions, ensuring high-performance mixed-signal/digital SoCs succeed from architecture to production. Responsibilities include trade studies, design standards, and vendor collaboration.

Lead verification of custom ASIC/SoC from block to full-chip: develop verification plans, build SystemVerilog/UVM testbenches, run constrained-random and directed tests, use SVA and formal methods, manage regressions and CI, drive coverage closure, support post-silicon bring-up, and influence DV methodology across cross-functional teams.

Define and execute verification plans for block-to-full-chip ASICs using SystemVerilog/UVM. Build testbenches, assertions, constrained-random and directed tests, manage regressions and CI, run simulations, triage failures, close coverage, and support silicon bring-up and post-silicon debug while collaborating across architecture, RTL, DFT, firmware, and physical design teams.

Lead DFT architecture and implementation for complex mixed-signal SoCs. Responsible for RTL-level scan and BIST insertion, ATPG flow development and coverage closure, mixed-signal test strategies, DFT verification and signoff, silicon bring-up support, and methodology/automation improvements while collaborating with design, verification, and physical design teams.

Lead development of behavioral models and mixed-signal verification methodology for analog/mixed-signal SoCs. Create Verilog/SystemVerilog/Verilog-AMS models, build co-simulation testbenches, integrate AMS into UVM digital environments, support architectural exploration, and drive cross-functional alignment with RF, analog, and digital teams to ensure successful silicon tapeout and bring-up.

Develop and execute verification plans for block, subsystem, and full-chip designs. Build SystemVerilog/UVM testbenches, write SVA, apply constrained-random and directed tests, run simulations, triage failures, drive root-cause analysis, maintain coverage and regression suites, and collaborate with cross-functional teams through sign-off.

The Principal GNC Engineer will drive spacecraft GNC architecture, perform verification and validation, develop tools and algorithms, and support launch operations, while mentoring engineers.