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The Senior ASIC Physical Design Engineer will oversee the full physical design flow for complex SoCs, ensuring timing closure and optimization while collaborating with various teams and external providers on satellite projects.

Lead the implementation of complex SoCs for satellite systems, managing the RTL-to-GDSII flow, collaborating with design teams, and ensuring silicon success in advanced technologies.

The Principal ASIC Design Verification Engineer is responsible for verifying custom silicon designs, developing verification plans, and collaborating with cross-functional teams on design-for-verification practices and silicon validation.

The Senior ASIC Design Verification Engineer will verify custom silicon designs, develop verification plans, drive test strategies, and collaborate with various engineering teams.

The ASIC Design Verification Engineer will verify silicon designs, develop verification plans, execute tests, and manage simulation environments, ensuring high quality and functionality through rigorous testing and collaboration with cross-functional teams.

The RFIC Layout Designer will lead the implementation of RF and mixed-signal ICs, focusing on layout strategies, top-level integration, and collaborating with various teams to ensure successful silicon tapeouts.

The Senior DFT Engineer will define and implement DFT architecture for mixed-signal SoCs, lead RTL-level DFT insertion, and collaborate with design teams to ensure high test coverage and manufacturability.

The Principal Digital ASIC Design Engineer will lead development of digital subsystems for SoCs, optimizing designs, collaborating on DSP implementations, and mentoring team members, ultimately contributing to spacecraft technology.

Lead a team of digital design engineers, manage ASIC design schedules, develop RTL for digital subsystems, and conduct verification and validation activities.

Lead the design and implementation of digital subsystems for state-of-the-art wireless SoCs for satellites, optimizing for power, performance, and area.