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Architect and build scalable cycle-accurate AI accelerator performance models for future hardware platforms, guiding design optimizations across various levels.

Responsible for physical design of high-performance CPUs and AI/ML architectures, including implementation from synthesis to tapeout, and collaborating with front-end teams.

Lead CTS methodology development for high-performance CPU and AI designs, optimizing clock architecture, performing design implementations, and collaborating with teams to resolve clocking challenges.

Lead the design and development of telemetry infrastructure for AI training and inference clusters. Analyze telemetry data to improve system design and operational practices.

Define and lead the architecture of IO chiplets integrating RISC-V CPUs and AI accelerators, ensuring robust specifications and interconnect compliance.

The Staff Engineer will develop and optimize physical design flows for AI silicon, automating implementation processes while collaborating with diverse teams.

The Campaign Producer will manage growth experiments through content creation, campaign management, marketing analytics, and cross-functional collaboration to optimize campaigns and drive audience engagement.

The Product Development Engineer role involves driving cost and quality in AI/ML architectures, conducting analyses, ensuring optimal production yield, and mentoring. Collaboration with cross-functional teams is essential.

The CPU Program Manager will oversee the end-to-end development of RISC-V CPUs, ensuring compliance with specifications, managing risks, and driving team collaboration.

Responsible for physical design tasks for high-performance CPUs, including synthesis, floorplanning, and optimizing power and area, while collaborating with RTL designers and engaging with customers.