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Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.

The HPC Architect will design and implement cutting-edge architectures for scientific and data-intensive applications, collaborating with engineers to optimize HPC performance.

The Staff DevOps Engineer will optimize infrastructure for chip development, build CI/CD pipelines, and enhance workflows using AI/ML practices.

The CPU Workload Performance Analysis Engineer will conduct workload characterization and performance simulation to optimize CPU products, collaborating with architects and designers.

The CPU Core Unit Lead will develop next-generation CPU RTL, define microarchitecture specifications, oversee design quality, mentor junior engineers, and use AI tools to enhance design processes.

Lead the physical design of high-performance CPUs and AI/ML chips, managing backend execution from RTL handoff to tapeout, while collaborating with various teams to optimize power, performance, and area.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Lead the go-to-market strategy by engaging with engineering-led customers, shaping product roadmaps, and creating scalable processes for early revenue traction.

This role involves managing enterprise accounts and overseeing the full sales lifecycle, aligning customer needs with AI solutions, and developing sales strategies.

The role involves defining and implementing CPU system RTL, collaborating with teams on delivering functional and efficient CPU designs, and optimizing power, performance, and area.