Top Tech Jobs & Startup Jobs in Denver & Boulder, CO

Lead as a hybrid Chief of Staff and execution-focused TPM for the RISC-V software org: define goals, plan and track execution, manage dependencies and risks, drive cross-functional initiatives, support headcount and recruiting, prepare leadership materials, and represent the team to partners and customers.

The Staff Technical Program Manager will lead semiconductor physical design projects, managing complex schedules and facilitating communication between teams and clients within AI/ML and CPU initiatives.

The STA Methodology Engineer will lead the optimization of timing methodologies and automation, collaborating across teams to address advanced-node design challenges.

Lead cross-functional product development for AI processors and systems from concept to delivery. Drive schedules, risks, dependencies, and stakeholder alignment across hardware, software, firmware, validation, manufacturing, and suppliers. Communicate technical status to executives and coordinate structured product development processes in a hybrid, collaborative environment.

Design board-level routing studies, mock-ups, and SI/PI modeling to support early-stage semiconductor package and package-board co-design. Collaborate with signal integrity, power integrity, mechanical, and system teams to develop PCB routing environments for BGA optimization, package escape studies, and system-level electrical modeling. Apply engineering judgment to evaluate tradeoffs and improve workflows using automation and data analytics.

Design and deliver die-to-die chiplet PHY IP in advanced FinFET nodes: develop PLLs and AMS blocks, lead design verification and layout interactions, support tape-out and silicon bring-up, and collaborate across architecture, digital, verification, layout, and software teams to achieve production-quality silicon.

Design and specify next-generation CPU networking for datacenter and automotive/robotics targets. Work at the intersection of NoC, performance modeling, and RTL to guide architecture, collaborate with hardware, software, and systems teams, and contribute to datacenter networking and early-stage automotive/robotics networking scoping and specifications.

The CPU Core Unit Lead will develop next-generation CPU RTL, define microarchitecture specifications, oversee design quality, mentor junior engineers, and use AI tools to enhance design processes.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.