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Implement and integrate DFT features including scan, JTAG, compression, ASST, and MBIST across ASIC IPs from RTL through tapeout. Own ATPG, test coverage analysis, gate-level simulation, and MBIST verification while developing DFx methodologies that integrate with front-end and physical design flows. Collaborate with design, physical design, verification, test, and manufacturing teams to optimize coverage, test cost, debug, yield learning, and silicon bring-up.

Develop and optimize automated test equipment programs for AI and compute silicon using the Advantest V93000. Responsibilities include creating modular test and measurement libraries, implementing parametric, functional, scan, BIST, and system-level tests, debugging failures, supporting silicon characterization, extracting Vmin/Fmax, defining production limits, and improving datalogging, yield analysis, test time, multisite efficiency, and measurement stability for NPI and high-volume manufacturing.

Develop and scale system-level test frameworks for AI silicon in high-volume manufacturing. Build test wrappers, harnesses, abstraction layers, telemetry, logging, failure signatures, and automated triage. Integrate functional, stress, and diagnostic tests while debugging issues across hardware, firmware, drivers, operating systems, and test equipment. Collaborate with validation, manufacturing, product engineering, and silicon teams to establish reliable execution, pass/fail criteria, and data standards for yield and RMA analysis.

Drive static timing analysis and timing convergence for multi-million-gate semiconductor designs on advanced process nodes. Develop constraints, timing models, closure strategies, ECOs, and automation flows; analyze violations across process corners and coordinate with Design and DFT teams through final signoff and tapeout.

Lead cross-functional technical programs for AI hardware and systems from concept through production. Coordinate hardware, software, firmware, validation, manufacturing, and supplier teams; manage schedules, risks, dependencies, and stakeholder communications; align teams around shared goals; and deliver complex products on schedule.

Physical Design Engineers at Tenstorrent are responsible for implementing high-performance AI SoC designs, overseeing the complete implementation flow from synthesis to tapeout and collaborating with cross-functional teams to ensure all design aspects are met.

As a Full-Chip Physical Design Verification Engineer, you will ensure manufacturable silicon by driving full-chip signoff, leading physical verification closure, and collaborating with various teams to achieve successful tapeouts.

The AI Subsystems Physical Design Lead is responsible for timing for subsystems in an AI chip, collaborating with RTL designers, and involved in synthesis, place and route, timing analysis, and power optimization.

The Physical Design Engineer will implement high-performance blocks for CPUs and AI/ML architectures, overseeing the entire flow from synthesis to tapeout and collaborating closely with teams to optimize performance, power, and area.

The Physical Design Engineer will lead efforts in solving physical design challenges, improve RTL-to-GDS methodologies, and integrate AI/ML solutions into CAD flows, focusing on performance and runtime improvements.