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Deep Learning Libraries engineer

Reposted 7 Days AgoSaved
Hybrid
2 Locations
Mid level
Mid level
Software
As a Deep Learning Libraries engineer, you will develop and optimize Deep Learning operators, collaborate with teams, and influence HW architecture for performance improvement.
Top Skills: CC++Deep LearningParallel ProgrammingPyTorch
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Rivos

Senior/Principal DL/LLM Performance Architect

Reposted 8 Days AgoSaved
Remote or Hybrid
3 Locations
Senior level
Senior level
Software
The role focuses on performance analysis, modeling, and validation for deep learning systems, enhancing both hardware and software responsiveness.
Top Skills: CC++CudaDeep LearningLarge Language ModelsLlvmMlirRisc-V
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Rivos

Senior Memory Design Engineer

Reposted 8 Days AgoSaved
Hybrid
2 Locations
Senior level
Senior level
Software
The Senior Memory Design Engineer will develop SRAM memories and custom circuits, ensuring high performance and low power design through collaboration and innovative problem-solving.
Top Skills: Circuit SimulationFinfetLec ToolsPpa AnalysisRtl-GdsSram
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Rivos

Post-Silicon Power Engineer

Reposted 8 Days AgoSaved
Hybrid
2 Locations
Mid level
Mid level
Software
Analyze power dissipation in server workloads, collaborate with teams to optimize power/performance ratio, and automate measurement infrastructure.
Top Skills: AssemblyCPythonShell Programming
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Rivos

DFT Engineer

Reposted 8 Days AgoSaved
Hybrid
2 Locations
Entry level
Entry level
Software
The DFT Engineer role involves designing DFT strategies, defining test structures, and ensuring designs meet DFT requirements while collaborating with various teams.
Top Skills: Ieee1500JtagMakefilesMbistPythonShell ScriptingSystemverilogTclVerilog
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Rivos

Accelerator DV Testgen

Reposted 8 Days AgoSaved
Hybrid
2 Locations
Junior
Junior
Software
Develop cutting-edge test generation strategies for validating accelerator designs, collaborating with hardware and software teams to create a variety of tests.
Top Skills: CC++CudaOpenclOpenglPythonRustSycl
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Rivos

Senior Memory Design Engineer

Reposted 8 Days AgoSaved
Hybrid
Fort Collins, CO, USA
Senior level
Senior level
Software
Develop custom SRAM and register file memories to enhance circuit performance. Collaborate across disciplines for design implementation and optimization.
Top Skills: Finfet TechnologyGdsLec ToolsRtlSram
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Rivos

Physical Design - Intern

Reposted 17 Days AgoSaved
In-Office
2 Locations
Internship
Internship
Software
Interns will handle block-level design tasks including RTL-to-GDSII transitions, timing closure, and collaborate with engineers on methodologies and design validation.
Top Skills: ClockingElectrical AnalysisFloorplanP&RPerlPlace & RoutePowerPythonSynthesisSystemverilogTclTimingUnixVerification Cad ToolsVerilog
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Rivos

Cache Microarchitecture & Logic Design

Reposted 17 Days AgoSaved
Hybrid
2 Locations
Mid level
Mid level
Software
The role involves designing cache microarchitecture, developing RTL designs, collaborating on physical designs, and validating performance metrics.
Top Skills: CC++Logic DesignMicroarchitectureRtl DesignSystemverilog
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Rivos

Silicon Formal Verification - Intern

Reposted 17 Days AgoSaved
In-Office
2 Locations
Internship
Internship
Software
The intern will assist in formal verification of a RISC-V core and accelerator designs, developing models, and verifying properties.
Top Skills: Formal VerificationModel CheckingRisc-VTheorem Provers
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