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Senior Memory Design Engineer

Reposted 4 Days AgoSaved
Hybrid
2 Locations
Senior level
Senior level
Software
The Senior Memory Design Engineer will develop custom SRAM and register file memories, focusing on performance and low power design while collaborating with various teams.
Top Skills: Circuit DesignCircuit SimulationDfmFinfet TechnologyLec ToolsLow Power Design TechniquesPpa AnalysisSramTransistor-Level Design
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Rivos

Senior/Principal DL/LLM Performance Architect

Reposted 4 Days AgoSaved
Remote or Hybrid
3 Locations
Senior level
Senior level
Software
Analyze and improve performance for deep learning workloads, develop analytical models, and validate performance for AI computing platforms.
Top Skills: C/C++CudaLlvmMlir
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Rivos

Post-Silicon Power Engineer

Reposted 4 Days AgoSaved
Hybrid
2 Locations
Mid level
Mid level
Software
Perform post-silicon power activities including power validation, workload analysis, and cross-functional collaboration to optimize power performance ratios.
Top Skills: AssemblyCLab Equipment (Multi-MeterOscilloscopes)PythonShell Programming
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Rivos

DFT Engineer

Reposted 4 Days AgoSaved
Hybrid
2 Locations
Junior
Junior
Software
The DFT Engineer will define DFT strategy, design DFT features, validate requirements, and collaborate with teams to ensure effective test coverage and debug observability.
Top Skills: AtpgDftIeee1500JtagMakefilesMbistPythonScanShell ScriptingSystemverilogTclVerilog
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Rivos

Deep Learning Libraries engineer

Reposted 4 Days AgoSaved
Hybrid
2 Locations
Mid level
Mid level
Software
The role involves developing and optimizing Deep Learning operator libraries and collaborating with cross-functional teams to enhance performance and efficiency of neural networks.
Top Skills: CC++PyTorch
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Rivos

Accelerator DV Testgen

Reposted 4 Days AgoSaved
Hybrid
2 Locations
Mid level
Mid level
Software
Develop advanced test generation strategies to validate accelerator design performance. Collaborate with teams, profile code, and debug testing issues.
Top Skills: CC++CudaOpenclOpenglPythonRustSycl
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Rivos

Senior Memory Design Engineer

Reposted 4 Days AgoSaved
Hybrid
Fort Collins, CO, USA
Senior level
Senior level
Software
Responsible for developing custom SRAM and register file memories, enhancing circuit performance, optimizing power, and collaborating across teams.
Top Skills: FinfetLec ToolsPpa AnalysisRtl-GdsSram
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Rivos

Accelerator Memory Subsystem Performance Modeling and Correlation

8 Days AgoSaved
Hybrid
2 Locations
Mid level
Mid level
Software
As an Accelerator Performance Architect, you'll define and model memory subsystem architectures, develop performance models, and analyze workloads in a team environment.
Top Skills: CC++PythonSystem-Verilog
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Rivos

SoC Performance Modeling

9 Days AgoSaved
Hybrid
2 Locations
Entry level
Entry level
Software
As a SoC Performance Modeling Engineer, you will design and implement performance models, validate them, analyze performance studies, and enhance modeling infrastructure.
Top Skills: C/C++PythonSystemverilog
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Rivos

DDR Memory Controller Verification

Reposted 11 Days AgoSaved
Hybrid
2 Locations
Mid level
Mid level
Software
As a Memory Controller Verification Engineer, you'll verify DDR and HBM memory subsystems, develop test plans, and collaborate with design teams and vendors.
Top Skills: Systemverilog,Uvm
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