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Rivos

SoC Performance Modeling

Reposted 3 Days Ago
Hybrid
2 Locations
Entry level
Hybrid
2 Locations
Entry level
As a SoC Performance Modeling Engineer, you will design and implement performance models, validate them, analyze performance studies, and enhance modeling infrastructure.
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Positions are open for full-time and internship in the areas of SoC performance modeling.

Responsibilities

  • As a SoC Performance Modeling Engineer, you will own or participate in the following: 
  • Work with architecture and design teams to design and implement the performance model
  • Validate the model and RTL performance model against the specification and correlate the model with RTL
  • Plan and analyze results of performance studies for different micro-architectural proposals
  • Rollup and present results and recommendations
  • Implement and enhance the performance modeling infrastructure
  • Provide feedback to the architecture and design teams regarding the micro-architectural choices that may have been made

Requirements

  • We are looking for all levels of talent, from entrance to advanced level of experience.
  • Strong knowledge in SoC architecture and performance trade-offs in areas of cache coherency, caches, DDR, PCIe/CXL, Ethernet, and/or NoCs
  • Proficient at SW programming with good understanding of C/C++, Python, and modular object oriented software development.
  • Knowledge of SystemVerilog and experience with simulators and waveform debugging tools is a plus
  • Experienced in SoC perf model development with good skills in performance analysis
  • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
  • Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

  • PhD, Master’s Degree or Bachelor’s Degree in technical subject area.

Top Skills

C/C++
Python
Systemverilog

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