The intern will assist in formal verification of a RISC-V core and accelerator designs, developing models, and verifying properties.
Positions are open for full-time and co-op/internship roles in the areas of formal verification of CPU, Fabric, and Accelerator design.
Responsibilities
- As a Formal Verification Engineer, you will be involved in the formal verification of the architecture and microarchitecture of a high-performance RISC-V core, a coherent fabric, and an accelerator design. In this position, you will:
- Work with architects and RTL design engineers to identify, specify, and verify artifacts amenable to formal analysis.
- Prove functional and security properties of the design, find design bugs, and work closely with design teams to deliver high-quality designs.
- Develop sound formal abstract models for verifying system-level properties like deadlock freedom and non-starvation using formal methods.
- Develop innovative flows using formal methods in conjunction with simulation-based techniques for effective bug hunting.
- Develop reusable and scalable proof techniques.
Requirements
- Understanding of formally specifying and analyzing temporal assertion properties.
- Experience with model checking/interactive theorem provers.
Education and Experience
PhD, Master’s Degree, or Bachelor’s Degree in a technical subject area.
Top Skills
Formal Verification
Model Checking
Risc-V
Theorem Provers
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