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The intern will work with designers on SOC verification, developing tests, analyzing coverage, and debugging simulations.

The intern will engage in CPU and SOC microarchitecture and logic design, focusing on RTL design, validation, and performance exploration.

The role involves measuring, analyzing, and improving the power and performance of deep learning workloads using both software and hardware backgrounds, requiring experience with simulators, benchmarking, and coding in various programming languages.

The role involves developing high-performance runtime libraries for GPGPU, collaborating with various teams to validate software with hardware, and extending tools for customers.

As a Senior Power-Management Architect, you will model and optimize power/performance features, define management features, and collaborate with teams for implementation and analysis.