Top Remote Senior Level Hardware Engineer Jobs in CO

Integrates first-party and third-party IPs into subsystems and SoCs using Verilog and SystemVerilog. Performs synthesis, timing constraint development, floor-planning analysis, performance optimization, register integration, CDC, lint, RDC, quality checks, and physical-design handoff. Works independently on complex integration problems, improves processes, supports junior staff, and communicates progress and status to customers regularly.

Perform transistor-level layout for RF, mixed-signal, and analog RFID IC blocks. Collaborate with analog and digital designers on floorplanning, pin placement, power distribution, routing, matching, electromigration, and signal coupling. Conduct layout reviews, resolve DRC/LVS/ERC issues, support advanced semiconductor process nodes, and coordinate layout schedules and floorplan activities.

The Senior Formal Verification Engineer will verify sophisticated ASIC builds using formal methods, collaborate with architecture teams, develop verification environments, and support silicon debug.

The PCB Layout Engineer will design complex printed circuit board layouts for drones, ensuring high performance, manufacturability, and reliability while collaborating with other engineering teams.

Develop and execute verification strategies for complex hardware IP, subsystems, and full-chip designs supporting Azure cloud servers. Responsibilities include writing test cases, simulators, and device specifications; evaluating verification tools; reviewing silicon architecture; managing schedules and risks; coordinating with internal and external teams; and contributing to training and technical leadership.

Designs complex RF printed circuit board layouts and schematics using Altium Designer. Creates component libraries, footprints, and 3D models; evaluates design feasibility, manufacturability, testing, cost, packaging, impedance control, and signal integrity. Coordinates with engineering, manufacturing, quality, test teams, and fabrication vendors throughout design release and production. Applies IPC standards, resolves fabrication issues, establishes design standards, and contributes to PCB design trade-offs and specifications.

Design and implement FPGA code for satellite digital payloads, including DSP algorithms, software-defined radio signal processing, embedded systems, and processor or peripheral interfaces. Responsibilities include developing custom IP, improving DSP and interface reliability, integrating vendor IP cores, supporting communications architecture, and participating in spacecraft design studies. The engineer will work across simulation, synthesis, place and route, timing closure, and hardware testing.

Design and optimize passive and active silicon photonic components from simulation through layout, foundry tapeout, and characterization. Perform electromagnetic and multiphysics simulations, analyze wafer-level measurement data, develop manufacturable designs, and collaborate with layout engineers, system-level PIC designers, and foundry partners. The role focuses on improving optical performance, fabrication tolerance, bandwidth, crosstalk, insertion loss, and power consumption for LiDAR and optical switching applications.

Develop and lead RF, SerDes, and mm-wave integrated circuits from architecture and simulation through silicon validation. Responsibilities include RF and analog IP design, layout guidance, characterization strategy, PCB development, RF and system-level measurements, competitive benchmarking, technology collaboration, productization, and university research liaison activities.

Supports and maintains mainframe hardware, including microcode, processor, storage, DASD, and tape configurations. Handles migrations, replication, disaster recovery, incident resolution, vendor escalations, and 24/7 on-call service restoration. Develops automation, tools, documentation, and standardized processes while supporting multiple clients in a leveraged environment. Performs ITIL change management, provides technical consulting, analyzes subsystem performance, and mentors team members.