Top Remote Senior Level Hardware Engineer Jobs in CO

Owner of micro-architecture and RTL lifecycle for complex digital blocks. Implement RTL in SystemVerilog/Verilog, drive control logic and IP integration, support sign-off (CDC, RDC, lint, synthesis), collaborate with DV teams for closure and debug, and take full project ownership with minimal supervision.

Lead RTL verification for RAIN RFID reader ICs across product lifecycle. Develop verification methodologies, SystemVerilog/UVM testbenches, BFMs, assertions, coverage metrics, CI/CD automation, and constrained-random tests. Collaborate with digital, analog, and silicon teams to ensure tape-out quality and support post-silicon validation and product improvements.

Lead architecture and microarchitecture of RISC-V CPU vector, floating-point, and matrix extensions. Translate HPC/AI workload needs into scalable CPU designs, optimize performance/power/area, define architectural specs, lead cross-functional teams from concept through silicon, and work on RTL development to enable efficient heterogeneous compute for AI/HPC.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.

Design and develop silicon photonics integrated circuits, driving architecture, product definition, and optimizing performance for optical systems while leading cross-functional collaboration.

Lead end-to-end development and launch of multiple hardware/firmware/software integrated product programs. Manage scope, schedules, budgets, and cross-functional global teams, drive commercialization and design transfer to manufacturing, mitigate risks, report status to leadership, ensure compliance with product development processes, and collaborate with supply chain, manufacturing, and customers.

Design and develop emulator-based chip-level validation and automated test infrastructure for HPE Slingshot NIC and switch ASICs. Author software-driven test content, debug hardware/software interactions, identify coverage gaps, support bring-up of new ASIC revisions, and collaborate with architecture, design, firmware, and software teams to validate functionality, performance, and reliability across product generations.

The Lead RTL/FPGA Design Engineer will develop and manage high-performance coherent modems for free space optical communications, translating DSP algorithms into synthesizable RTL, ensuring compliance, and supporting integration and testing.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.

Lead build, integration, and optimization of full-chip and system-level ASIC emulation platforms. Enable HW/SW co‑development, debug emulation failures, automate compile/regression flows, support silicon bring-up, and collaborate with RTL, DV, firmware, physical design, and validation teams to accelerate verification and system validation.