Top Remote Senior Level Hardware Engineer Jobs in CO

The Senior Mechanical Engineer will design and develop consumer products, collaborate with teams, and lead mechanical engineers in creating and testing innovative technologies.

The Senior Mechanical Engineer will design mechanical systems for data centers, ensuring reliability, efficiency, and scalability while collaborating with various teams.

As an ASIC Design Verification Engineer, you will develop and execute verification strategies for AI inference ASICs, ensuring functional correctness and performance, while collaborating with design and architecture teams.

The PIC Architect is responsible for designing advanced silicon photonics integrated circuits, managing PIC development, and coordinating with cross-functional teams to optimize performance and manufacturing processes.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.

The Sr. Hardware Design Engineer leads ASIC and FPGA projects, defining architecture, guiding RTL development, and mentoring junior engineers to deliver high-quality silicon solutions.

Responsible for semiconductor technology component engineering for CommIC products, managing design-in, testing, manufacturing, and quality, while interfacing with suppliers and internal teams to resolve issues.

The Senior DFT Engineer will define and implement DFT architecture for mixed-signal SoCs, lead RTL-level DFT insertion, and collaborate with design teams to ensure high test coverage and manufacturability.

The Senior Principal Hardware Systems Engineer leads architecture of high-performance compute platforms, focusing on PCIe design, GPU integration, and system-level development, while managing cross-functional teams and vendor collaboration.

The Lead RTL/FPGA Design Engineer will develop and manage high-performance coherent modems for free space optical communications, translating DSP algorithms into synthesizable RTL, ensuring compliance, and supporting integration and testing.