Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.
This role is hybrid, based out of Austin, Santa Clara, or Fort Collins.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
- Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
- Strong problem solver who excels at debugging complex issues across design hierarchies.
- Collaborative team player who thrives in fast-paced, technically challenging environments.
What We Need
- BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.
- Expertise with industry-standard tools (Innovus, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
- Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).
- Experience driving physical design requirements from early architecture through final signoff.
What You Will Learn
- How to implement cutting-edge AI accelerators and high-performance CPUs on the most advanced process nodes.
- Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures.
- End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams.
- Direct impact on products that are redefining the landscape of AI and high-performance computing.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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