Jobs at Tenstorrent Inc.

Lead cross-functional product development for AI processors and systems from concept to delivery. Drive schedules, risks, dependencies, and stakeholder alignment across hardware, software, firmware, validation, manufacturing, and suppliers. Communicate technical status to executives and coordinate structured product development processes in a hybrid, collaborative environment.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.

Physical Design Engineers at Tenstorrent are responsible for implementing high-performance AI SoC designs, overseeing the complete implementation flow from synthesis to tapeout and collaborating with cross-functional teams to ensure all design aspects are met.

Responsible for physical design of high-performance CPUs and AI/ML architectures, including implementation from synthesis to tapeout, and collaborating with front-end teams.

As a Full-Chip Physical Design Verification Engineer, you will ensure manufacturable silicon by driving full-chip signoff, leading physical verification closure, and collaborating with various teams to achieve successful tapeouts.

The AI Subsystems Physical Design Lead is responsible for timing for subsystems in an AI chip, collaborating with RTL designers, and involved in synthesis, place and route, timing analysis, and power optimization.

The Physical Design Engineer will implement high-performance blocks for CPUs and AI/ML architectures, overseeing the entire flow from synthesis to tapeout and collaborating closely with teams to optimize performance, power, and area.

The Physical Design Engineer will lead efforts in solving physical design challenges, improve RTL-to-GDS methodologies, and integrate AI/ML solutions into CAD flows, focusing on performance and runtime improvements.

The Staff Technical Program Manager will lead semiconductor physical design projects, managing complex schedules and facilitating communication between teams and clients within AI/ML and CPU initiatives.

The STA Methodology Engineer will lead the optimization of timing methodologies and automation, collaborating across teams to address advanced-node design challenges.

Design board-level routing studies, mock-ups, and SI/PI modeling to support early-stage semiconductor package and package-board co-design. Collaborate with signal integrity, power integrity, mechanical, and system teams to develop PCB routing environments for BGA optimization, package escape studies, and system-level electrical modeling. Apply engineering judgment to evaluate tradeoffs and improve workflows using automation and data analytics.

Contract Technical Recruiter (12-month, hybrid in Austin) partnering with engineering leaders to source, attract, and hire AI/ML, systems software, and hardware engineering talent. Build hiring strategies, talent pipelines, and targeted sourcing campaigns, deliver a high-touch candidate experience, and share market intelligence to improve recruiting outcomes.

Design and specify next-generation CPU networking for datacenter and automotive/robotics targets. Work at the intersection of NoC, performance modeling, and RTL to guide architecture, collaborate with hardware, software, and systems teams, and contribute to datacenter networking and early-stage automotive/robotics networking scoping and specifications.

The CPU Core Unit Lead will develop next-generation CPU RTL, define microarchitecture specifications, oversee design quality, mentor junior engineers, and use AI tools to enhance design processes.

Design and deliver die-to-die chiplet PHY IP in advanced FinFET nodes: develop PLLs and AMS blocks, lead design verification and layout interactions, support tape-out and silicon bring-up, and collaborate across architecture, digital, verification, layout, and software teams to achieve production-quality silicon.

Define architecture and micro-architecture specs for memory and I/O chiplets, evaluate next-generation memory technologies, develop performance and power modeling infrastructure, and collaborate with SoC, verification, physical design, packaging, systems teams and external partners to enable high-throughput, low-latency memory architectures.

Lead hardware-software co-design to enable AI/HPC and agentic AI stacks on RISC-V CPUs. Integrate and optimize low-level kernel infrastructure, runtimes, distributed execution, memory systems, and developer tools, collaborating with architects, compiler engineers, and kernel developers to meet performance targets.

Lead and enhance global People Operations, focusing on employee lifecycle management, operational excellence, and compliance across multiple regions.

As a Chip Design Lead at Tenstorrent, you will oversee the development of SoC programs from architecture to deployment, ensuring collaboration across teams and managing chip lifecycle processes.