Jobs at Tenstorrent Inc.

Physical Design Engineers at Tenstorrent are responsible for implementing high-performance AI SoC designs, overseeing the complete implementation flow from synthesis to tapeout and collaborating with cross-functional teams to ensure all design aspects are met.

Responsible for physical design of high-performance CPUs and AI/ML architectures, including implementation from synthesis to tapeout, and collaborating with front-end teams.

As a Full-Chip Physical Design Verification Engineer, you will ensure manufacturable silicon by driving full-chip signoff, leading physical verification closure, and collaborating with various teams to achieve successful tapeouts.

The AI Subsystems Physical Design Lead is responsible for timing for subsystems in an AI chip, collaborating with RTL designers, and involved in synthesis, place and route, timing analysis, and power optimization.

The Physical Design Engineer will implement high-performance blocks for CPUs and AI/ML architectures, overseeing the entire flow from synthesis to tapeout and collaborating closely with teams to optimize performance, power, and area.

The Physical Design Engineer will lead efforts in solving physical design challenges, improve RTL-to-GDS methodologies, and integrate AI/ML solutions into CAD flows, focusing on performance and runtime improvements.

The Staff Technical Program Manager will lead semiconductor physical design projects, managing complex schedules and facilitating communication between teams and clients within AI/ML and CPU initiatives.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.

Design and deliver die-to-die chiplet PHY IP in advanced FinFET nodes: develop PLLs and AMS blocks, lead design verification and layout interactions, support tape-out and silicon bring-up, and collaborate across architecture, digital, verification, layout, and software teams to achieve production-quality silicon.