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Flux Computing

Senior / Staff Analog Design Engineer - High Speed SerDes

Reposted 11 Days Ago
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In-Office
Austin, TX
194K-270K Annually
Senior level
In-Office
Austin, TX
194K-270K Annually
Senior level
Design and verify high-speed SerDes interfaces, develop CDR loops, optimize signal integrity, and mentor junior engineers within a fast-paced environment.
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Flux Computing designs and manufactures optical processors to train and run inference on large AI models. Join us to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed.

The Role

We are seeking an experienced Analog /RF IC designer to architect, implement and productise the multi‑lane, multi‑standard SerDes (serialiser / deserialiser) interfaces that move data in and out of the OTPU at tens of gigabits per second per lane. You will own both transmit and receive paths—equalisers, CDRs, drivers, samplers and clocking assist blocks—while ensuring robust operation over challenging channels and across multiple aggregated lanes. Your designs will be central to realising Flux’s multi‑terabit‑per‑second optical fabric.

Responsibilities

  • Define, design and verify SerDes cores operating at >25Gb/s‑per‑lane, including TX FIR/DFE equalisation, CTLE/FFE receivers, decision‑feedback paths, and high‑linearity output drivers.

  • Develop adaptive clock‑data‑recovery (CDR) loops and multi‑lane deskew / phase‑alignment schemes that achieve < 200 fs rms additive jitter and < 5 ps lane‑to‑lane skew.

  • Model channel losses (PCB, package, fibre) and work with signal‑integrity engineers to co‑optimise link budgets, impedance control and return‑loss targets.

  • Partner tightly with analog designers photonic, packaging, and digital micro‑architecture teams to integrate SerDes IP into large chiplets and optical transceiver modules.

  • Mentor junior engineers, conduct rigorous design reviews, and establish best‑practice flows for high‑speed mixed‑signal design, verification and lab characterisation.

Skills & Experience

  • 7 + years of industry experience designing production high‑speed SerDes, multi‑GHz CDRs, or comparable mixed‑signal I/O macros in advanced CMOS nodes.

  • Demonstrated success taping out > 56 Gb/s links meeting BER < 10‑12, stringent jitter masks and channel compliance specs.

  • Deep understanding of link‑level signal‑integrity, phase noise, adaptive equalisation, clock multiplication and on‑chip calibration techniques.

  • Mastery of state‑of‑the‑art EDA flows: behavioral modeling (Verilog‑A/AMS, IBIS‑AMI), transient / S‑parameter simulation, EM extraction, and mixed‑signal verification.

  • Strong measurement skills: high‑speed probing, BERT eye‑diagramming, de‑embedding, PRBS and compliance testing.

  • Bachelor’s degree in Electrical Engineering or related field (Master’s / PhD preferred).

  • Excellent cross‑disciplinary communication, problem‑solving aptitude, and a proven ability to deliver in fast‑moving, innovation‑driven environments.

  • A portfolio of patents, publications or open‑source contributions that highlights creative SerDes or high‑speed analog design insight.

Compensation & Benefits

  • $194,000 – $270,000 + annual salary, depending on experience, skills, and location.

  • Competitive stock options, you’re not just part of the journey, you will own a piece of it.

  • Work from our office in The Domain, right in buzzing Austin with parking available for easy access.

  • Live within 45 minutes of the office? Perfect. Live within 20 minutes? We’ll add an extra location bonus ($24K) to your salary.

  • We offer financial and operational relocation support (US and abroad), through a dedicated third-party provider who is on hand to make your move to Austin as seamless as possible.

  • We offer visa sponsorship so if we make you an offer we will make every reasonable effort to secure you a visa, but we may not be able to sponsor visas for every role and candidate.

  • We’re in the process of setting up a US group policy once we have 5+ employees. In the meantime, we’re providing a health insurance stipend of $800/month to offset costs. Once the group policy is live, Flux will cover 100% of the employee premium, and offer options like dental, vision and life insurance with an aim to remain competitive among Austin tech and start up employers.

  • We offer US employees access to a 401(k) retirement savings plan and we plan to introduce an employer match in line with Austin tech market norms (commonly in the 4-5% range). Our goal is to keep our retirement benefits competitive while we scale.

  • Top of the line, high-spec tech for everyone.

  • Sony noise-cancelling headphones and ergonomic setups to keep you comfortable and focused.

  • Personal company card to spend on tools that help you do your job - like ChatGPT Pro or anything else that boosts your workflow.

  • Periodic travel to London HQ and regular team socials.

  • 33 days of paid time off (PTO), including US federal holidays.

Due to U.S. export control regulations, candidates’ eligibility to work at Flux depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.

We do not accept unsolicited CVs from recruitment agencies, will not be liable for any fees, and prohibit unauthorised use of our company name in recruitment activities.

We’re building fast and that includes our benefits. More exciting additions are coming soon for the Flux crew.

If you are passionate about pushing the boundaries of what's possible in AI and thrive in a high-energy, fast-paced environment, we want to hear from you. Apply now to join Flux and be a key player in shaping the future of computing.

Top Skills

Ams
Cdrs
Cmos
Ibis-Ami
Mixed-Signal Verification
Serdes
Verilog-A

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