Senior Physical Design Methodology Engineer, PPA Fusion Compiler

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer(s) - PPA Fusion Compiler to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

• Developing Efficient physical design methodologies for implementation of graphics processors and SOCs.

• Key responsibility includes developing unique and creative solutions to the state-of-the-art physical design problems to improve PPA

• Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis and back-end verification across multiple projects along with chip floorplan, power and clock distribution, chip assembly.

• Extensive timing knowledge to support timer for implementation to convergent implementation.

• Data based analysis and algorithmic solutions for PPA check and improvement.

What we need to see:

• MS in Electrical or Computer Engineering (or equivalent experience)

• Minimum 5 years’ experience in Physical Design Engineering

• Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.

• Staring knowledge of Physical design with convergence in timing/EM/IR with best PPA

• Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence.

• Familiar with various process related design issues including Design for Yield and Manufacturability, EM and IR closure and thermal management.

• Solid understanding of industry standard PnR tools and analysis tools, Capable of extensive scripting to check and improve PPA

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.Applications for this job will be accepted at least until July 29, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.