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Deepgram

Embedded AI Engineer, On-Device Models

Posted An Hour Ago
Remote
Hiring Remotely in USA
219K-274K Annually
Senior level
Remote
Hiring Remotely in USA
219K-274K Annually
Senior level
Take Deepgram's speech models and optimize, compile, and run them on resource-constrained embedded and edge hardware. Work across model compression, runtime performance (C/C++/Rust), RTOS/bare-metal and embedded Linux environments, vendor NPUs/DSPs and inference runtimes, benchmarking, deployment pipelines, OTA updates, and partner with silicon vendors to enable real-time, low-power on-device voice experiences.
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Company Overview

Deepgram is the leading platform underpinning the emerging trillion-dollar Voice AI economy, providing real-time APIs for speech-to-text (STT), text-to-speech (TTS), and building production-grade voice agents at scale. More than 200,000 developers and 1,300+ organizations build voice offerings that are ‘Powered by Deepgram’, including Twilio, Cloudflare, Sierra, Decagon, Vapi, Daily, Cresta, Granola, and Jack in the Box. Deepgram’s voice-native foundation models are accessed through cloud APIs or as self-hosted and on-premises software, with unmatched accuracy, low latency, and cost efficiency. Backed by a recent Series C led by leading global investors and strategic partners, Deepgram has processed over 50,000 years of audio and transcribed more than 1 trillion words. There is no organization in the world that understands voice better than Deepgram.

Company Operating Rhythm

At Deepgram, we expect an AI-first mindset—AI use and comfort aren’t optional, they’re core to how we operate, innovate, and measure performance.

Every team member who works at Deepgram is expected to actively use and experiment with advanced AI tools, and even build your own into your everyday work. We measure how effectively AI is applied to deliver results, and consistent, creative use of the latest AI capabilities is key to success here. Candidates should be comfortable adopting new models and modes quickly, integrating AI into their workflows, and continuously pushing the boundaries of what these technologies can do.

Additionally, we move at the pace of AI. Change is rapid, and you can expect your day-to-day work to evolve just as quickly. This may not be the right role if you’re not excited to experiment, adapt, think on your feet, and learn constantly, or if you’re seeking something highly prescriptive with a traditional 9-to-5.

About the Role

Deepgram's speech AI models are among the fastest and most accurate in the world — and the next wave of voice experiences won't live only in the cloud. They'll run directly on the small, low-power devices people carry, wear, and keep around their homes: phones, earbuds, wearables, appliances, cameras, and purpose-built consumer hardware. Putting state-of-the-art speech models on devices with tight memory, compute, thermal, and battery budgets is a fundamentally different engineering problem, and it's one of the most important frontiers for bringing voice AI to everyone.

As an Embedded AI Engineer, you will take Deepgram's models and make them run — fast, accurately, and efficiently — on resource-constrained embedded and edge platforms. You'll work across the stack: optimizing and compiling models for on-device inference, writing performance-critical runtime code, and squeezing every last millisecond and milliwatt out of a wide range of mobile application processors, embedded SoCs, microcontrollers, and dedicated AI accelerators. Your work directly enables a new class of private, offline-capable, real-time voice experiences on the devices closest to the user.

This role is a great fit whether you're a hands-on senior embedded engineer who wants to go deep on a hard problem, or a staff-level technical leader who wants to define how Deepgram's voice AI gets onto consumer hardware and raise the bar for the engineers around you. We'll set the level to your experience.

What You'll Do
  • Take Deepgram's Speech and Conversational models and get them running on embedded and low-power consumer hardware — defining the architecture for on-device, real-time inference across a diverse range of processors and accelerators.

  • Optimize models for constrained targets through quantization, pruning, distillation, operator fusion, and architecture-specific compilation to meet strict latency, memory, power, and thermal budgets.

  • Write and optimize performance-critical runtime code (C, C++, and/or Rust) for embedded environments, including bare-metal and real-time operating systems such as FreeRTOS and Zephyr.

  • Integrate with industry-standard edge inference runtimes and vendor NPU/DSP toolchains, mapping model graphs efficiently onto on-device accelerators and CPU/GPU/NPU heterogeneity.

  • Build the on-device runtime plumbing: model packaging, deployment pipelines, over-the-air update mechanisms, and lightweight telemetry for devices operating with limited or intermittent connectivity.

  • Establish repeatable benchmarking and validation across target hardware — measuring latency, accuracy, power consumption, memory footprint, and resource utilization — and catch regressions before they ship.

  • Partner with silicon and device vendors on SDK integration and performance tuning, getting our models to run efficiently on new chipsets and reference platforms.

  • Collaborate with Research and Engine teams to influence model architectures toward edge-friendly designs from the start, reducing the optimization burden at deployment time.

You'll Love This Role If You
  • Find deep satisfaction in making a large model run on a tiny device — and still hit accuracy and latency targets.

  • Want to work at the intersection of AI and hardware, where optimization isn't optional but existential.

  • Are energized by the back-and-forth of getting a model to sing on a new chipset, runtime, or accelerator.

  • Believe on-device AI is the next major deployment frontier and want to define how speech AI gets there for consumers.

  • Prefer hard, constrained, ship-it problems over open-ended research — you want to see your work running in people's hands.

  • Care about the details that don't show up in a cloud benchmark: cold-start time, power draw, thermals, and memory fragmentation.

It's Important To Us That You Have
  • Experience delivering production systems on resource-constrained hardware — embedded systems, mobile, edge AI, or small low-power devices.

  • Strong proficiency in C, C++, and/or Rust, with experience writing performance-critical code for constrained environments.

  • Hands-on experience with model optimization for on-device deployment, including quantization, pruning, knowledge distillation, or architecture-specific compilation.

  • Familiarity with edge inference runtimes (e.g., ONNX Runtime, TensorRT, TFLite, ExecuTorch) and/or vendor-specific NPU/DSP toolchains.

  • A strong understanding of hardware-software interaction — CPU/GPU/NPU/DSP architectures, memory hierarchies, fixed-point/integer arithmetic, and power management — and how they affect inference performance.

  • Experience working close to the metal: bare-metal or RTOS environments (e.g., FreeRTOS, Zephyr), embedded Linux, or microcontroller and edge SoC development.

  • Strong communication skills and a builder mindset — you can scope an ambiguous optimization problem, drive it to a measurable result, and explain the tradeoffs clearly.

It Would Be Great if You Had
  • Experience with real-time audio processing on embedded platforms — DSP pipelines, audio codec optimization, wake-word or always-on listening, or streaming inference on microcontrollers and edge SoCs.

  • Depth in ML optimization techniques — custom quantization schemes, mixed-precision inference, or neural architecture search for edge targets.

  • Background in hardware evaluation and benchmarking — systematically comparing accelerators, SoCs, or GPUs for specific workload profiles.

  • Experience shipping AI features in consumer products at scale, and the instinct for what "production quality" means on a battery-powered device.

  • Familiarity with model compilation and optimization toolchains and their tradeoffs across hardware targets.

  • Experience with secure, robust on-device deployment practices — code signing, encrypted model storage, and safe update mechanisms.

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