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Intel

EDA Tools Hardware Engineer

Posted 11 Days Ago
Be an Early Applicant
7 Locations
140K-197K Annually
Mid level
7 Locations
140K-197K Annually
Mid level
The role involves designing and optimizing hardware, enhancing design productivity, and working with EDA tools and methodologies, with a focus on backend flow and modern process nodes.
The summary above was generated by AI

Job Details:

Job Description: 

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below.

 

Life at Intel

Diversity at Intel

 

 

CCG is a computing paradigm where services and data reside in scalable data centers, and those services and data can be accessed by any connected device over the Internet. Responsible for designing and optimizing processors, chipsets and other hardware for consumer devices while also working on the software ecosystem, including drivers and utilities that enhance user experience.

Your responsibilities may include, but are not limited to:

  • Delivering world-class Tools, Flows and Methodologies (TFM) to Intel's IP, Core, and
  • SoC product design teams
  • Performing Power/Performance/Area trade-off exploration and analysis
  • Enabling leading edge process technologies on Intel and external foundries
  • Enhancing design team productivity by increasing throughput, reducing iterations, and enabling larger and larger blocks
  • Working on cutting edge technologies such as Machine Learning / AI and Cloud

 

                                                     

Important behavior attributes:

  • Ability to create and drive concepts to innovative solutions
  • Excellent verbal communication and interpersonal skills that will be a role-model for the team and the broader organization.
  • Analytical and problem-solving skills
  • Effective team player with continuous learning mindset

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
What we need to see (Minimum Qualifications):

  • Bachelor's degree in Electrical/Computer Engineering, Computer Science or related major with 3+ years experience -OR- Master's degree in Electrical/Computer Engineering, Computer Science or related major with 2+ years’ experience.
  • 2+ years’ experience driving new initiatives, leading on-time technical deliverables, tracking and execution resulting in successful enablement of CAD flows for product tape-outs.
  • 2+ years’ experience in backend flow design and implementation using Synopsys or Cadence tools, debug, support.
  • 2+ years’ experience scripting (such as TCL/Perl/Python).
  • 2+ years’ experience developing and delivering backend EDA tool/CAD design flows and methodologies with at least two generations of modern process node experience (3nm, 5nm, 7nm).

 

 

Preferred Qualifications:

  • Master's or PHD degree in Electrical/Computer Engineering, Computer Science or related major with 4+ years’ experience.
  • Good depth and breadth of understanding of logic design concepts, floorplan, structural design, clocking, layout, extraction and timing aspects of complex digital designs.
  • Prior experience in technical leadership in execution of complex SOCs would be a plus.
  • Direct hands-on experience in one or more of the following areas:
  • Machine Learning (ML) and/or Artificial Intelligence (AI). (Synopsys DSO, Cadence Cerebrus)
  • EDA/CAD vendor tools (Synopsys (PrimeTime, Fusion Compiler), Cadence tools (Innovus, Genus, Tempus)
  • Design creation/convergence, Sign Off, and Closure Flows (Extraction, Timing, Power, Noise, ERC, RV, and Formal Equivalence)
  • Circuit design and process technology.

 

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

 

 

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Folsom

Additional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Colorado, Fort Collins, US, Massachusetts, Hudson, US, Oregon, Hillsboro, US, Texas, Austin

Business group:Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$139,710.00-$197,230.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

The application window for this job posting is expected to end by 06/20/2025

Top Skills

Cadence
Perl
Python
Synopsys
Tcl

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