DFT Design Engineer

Job Details:

Job Description: 

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

A nimble, fast-paced Design for Test (DFT) team responsible for achieving high levels of DFT quality on server and/or AI related SOC products.

Who You Are

Responsibilities include but are not limited to:

• Develops the logic design, register transfer level (RTL) coding, and simulation for a SoC Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).

• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).

• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).

• Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.

• Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.

• Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.

• Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.

• Collaborates with post silicon and manufacturing team to verify the features on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.

• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
 

Minimum Qualifications

Bachelor's Degree in Electrical Engineering, computer science or related field with 3+ years of industry experience OR Master's Degree in Electrical Engineering, computer science or related field with 2+ years of industry experience

Technical Experience:

• 3+ years of experience with DFT

• 1+ years of experience with Synopsys or Cadence tools

Preferred Qualifications

• ATPG expertise

• Primetime expertise, especially in DFT constraints

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Colorado, Fort Collins

Additional Locations:US, California, Santa Clara, US, Massachusetts, Hudson, US, Oregon, Hillsboro, US, Texas, Austin

Business group:The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$139,710.00-$197,230.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

The application window for this job posting is expected to end by 04/23/2026