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Tenstorrent Inc.

Customer IP Enablement Engineer

Reposted 12 Days Ago
Be an Early Applicant
In-Office
3 Locations
100K-500K
Mid level
In-Office
3 Locations
100K-500K
Mid level
Responsible for physical design tasks for high-performance CPUs, including synthesis, floorplanning, and optimizing power and area, while collaborating with RTL designers and engaging with customers.
The summary above was generated by AI

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Physical design for high-performance designs going into industry leading CPU and AI/ML architecture. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done alongside a group of highly experienced engineers across various domains of the AI chip.

This role is hybrid, based out of Santa Clara, CA, Fort Collins, CO or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.


Responsibilities:

  • Own physical design for multiple variants of the IP to be delivered to customers
  • Physical design tasks including such as synthesis, PnR, area improvement, floorplanning, clocking, I/O planning and power optimization
  • Develop and own physical design integration guide for the IP
  • Engage with IP customers and address PPA related concerns
  • Collaborate with RTL designers to explore design options for achieving optimal PPA

Experience & Qualifications:

  • BS/MS/PhD in EE/ECE/CE/CS
  • Expertise in optimizing PPA for high performance and low power designs
  • Prior experience with optimizing RTL for timing/power
  • Hands-on experience with synthesis, block and chip level implementation flows
  • Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
  • Strong programming skills in Tcl/Perl/Shell/Python
  • Knowledge of CPU Micro Architecture is a plusZPrior experience working with customers is an asset

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Top Skills

Perl
Python
Shell
Tcl

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