Senior Physical Design Engineer - CTS

CTS Methodology Lead for high-performance designs going into industry leading CPU and AI/ML architecture. This role involves owning and driving CTS methodology development and implementation, and help define and refine clock architecture strategies (e.g., traditional CTS, H-tree, mesh) for a variety of high-performance designs.

This role is hybrid, based out of Santa Clara, CA, Austin, TX or Ft. Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Own and drive CTS methodology development and implementation, ensuring industry-leading clock quality and performance.
• Define and refine clock architecture strategies (e.g., traditional CTS, H-tree, mesh) for a variety of high-performance designs.
• Utilize physical design tools (PNR) to design, implement, and optimize complex clock trees.
• Optimize clock non-default rules (NDRs) to achieve minimal insertion delays, skew, and maximize overall power, performance, and area (PPA).
• Remain hands-on with timing closure processes and collaborate with RTL, DFT, and physical implementation teams to resolve clocking challenges.
• Evaluate and benchmark new CTS flows and tools; contribute to tool evaluations and methodology improvements.
• Document methodologies and best practices; provide guidance and training to design teams.
• Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks, and design closure.

Experience & Qualifications:

• BS/MS/PhD in Electrical Engineering, Electronics, Computer Engineering, or Computer Science.
• 5–10 years of relevant industry experience in physical design and CTS implementation.
• Prior experience executing designs at leading edge technology nodes
• Proven experience owning and delivering CTS for complex, high-performance ASIC or SoC designs.
• Proficient in using place-and-route (PNR) tools for clock implementation and optimization.
• Strong understanding of clocking methodologies, including mesh, H-tree, and traditional CTS strategies.
• In-depth expertise in optimizing clock non-default rules (NDRs) for minimal insertion delay, skew, and improved PPA.
• Familiarity with DFT clocking concepts is highly desirable.
• Hands-on experience with synthesis and place and route using industry standard tools
• Strong programming/scripting skills in Tcl, Perl, Shell, and Python.
• Excellent verbal and written communication skills; collaborative attitude.
• Ability to thrive in a fast-paced, innovative environment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.