Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Lead the physical design of cutting-edge CPUs and AI/ML chips from synthesis through tapeout. In this role, you’ll own high-performance IP implementation and work closely with front-end, architecture, and backend teams to push power, performance, and area boundaries.
This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Fort Collins, CO.
We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- An experienced physical design engineer with a background in SoC, CPU, GPU, or AI/ML implementations.
- Confident managing backend execution from RTL handoff through signoff and tapeout.
- Skilled in timing closure, floorplanning, and physical implementation techniques.
- Comfortable writing scripts and debugging across design hierarchies.
What We Need
- Engineers with hands-on experience using Innovus, Primetime, RedHawk, and similar tools.
- Deep understanding of PnR, timing analysis, area and power optimization, and ECO closure.
- Ability to define physical design requirements and partner effectively with RTL and architecture teams.
- Familiarity with low-power techniques and experience working at advanced technology nodes.
What You Will Learn
- The end-to-end physical implementation process for next-generation AI and CPU architectures.
- How to run and evaluate experiments across RTL, synthesis, and layout to optimize for PPA.
- How expert teams collaborate across RTL, verification, DFT, and software to deliver high-impact silicon.
- Best practices for automating flows and solving challenges at deep sub-micron nodes.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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