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Tenstorrent Inc.

Sr. Staff, Physical Design Engineer - Chiplets

Reposted Yesterday
Be an Early Applicant
Remote
Hiring Remotely in United States
100K-500K
Junior
Remote
Hiring Remotely in United States
100K-500K
Junior
The role involves high-speed CPU core integration from RTL to silicon, focusing on PnR, timing, and collaboration for chiplet systems.
The summary above was generated by AI

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We're building fast silicon and integrating it into a chiplet-based system — and we need people who can help close that loop. This isn’t just a PnR role — it’s about owning the last mile between great architecture and real silicon. If you know physical design or want to level up fast in it, and care about making hard things work, we’ve got room at the table.

This role is hybrid based out of Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.


Who You Are 

  • Deeply curious about how high-performance silicon gets built and delivered.
  • Comfortable in the weeds — timing reports, power grids, clock trees, layout blocks.
  • Interested in how chiplets change physical design, integration, and packaging.
  • A builder who sees constraints as part of the fun, not a reason to back off.

What We Need

  • An engineer to help bring high-speed CPU cores from RTL to physical silicon.
  • Someone comfortable working across synthesis, place & route, timing, and signoff to ensure clean chiplet integration.
  • A strong collaborator who can align physical implementation with architectural and verification intent.
  • A practical problem-solver who improves slow parts of the flow, automates what’s repetitive, and catches issues early.

What You Will Learn

  • How chiplet architecture reshapes the rules of physical design and timing.
  • What it takes to build a system where the silicon, packaging, and performance all align.
  • Why real closure isn’t about tools — it’s about understanding the system.
  • How a tightly integrated team moves fast across disciplines and tapeouts.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Top Skills

Chiplet Integration
Clock Trees
Physical Design
Place & Route
Power Grids
Risc-V
Rtl
Synthesis
Timing
Timing Reports

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