Teams at Broadcom

Develop and integrate SoC architectures and embedded IP for AI and storage chips. Responsibilities include design analysis, simulation, synthesis, formal verification, validation, timing and physical implementation optimization, and release documentation. The role coordinates internal and external teams, collaborates with layout and DFT engineers, and makes data-driven architectural trade-offs involving processors, AMBA interconnects, IO, DRAM, and high-speed SERDES.

Owns and supports PVD equipment in an 8-inch semiconductor wafer fabrication facility. Responsibilities include equipment troubleshooting, optimization, upgrades, conversions, preventative and predictive maintenance, qualification, personnel training, and performance monitoring. The role collaborates with process engineering and R&D to develop robust equipment and processes, apply statistical validation, and execute improvement projects supporting high-volume manufacturing.

Performs end-to-end physical IC design from RTL through silicon tape-out, including synthesis, physical verification, timing closure, EM/IR analysis, place and route, clock tree synthesis, floorplanning, layout, and methodology development. Collaborates with RTL engineers and develops physical design flows using TCL/Perl scripting and EDA tools. The role is fully onsite and supports PCIe switch and enterprise storage products.