Jobs at Broadcom

Develop and integrate SoC architectures and embedded IP for AI and storage chips. Responsibilities include design analysis, simulation, synthesis, formal verification, validation, timing and physical implementation optimization, and release documentation. The role coordinates internal and external teams, collaborates with layout and DFT engineers, and makes data-driven architectural trade-offs involving processors, AMBA interconnects, IO, DRAM, and high-speed SERDES.

Owns and supports PVD equipment in an 8-inch semiconductor wafer fabrication facility. Responsibilities include equipment troubleshooting, optimization, upgrades, conversions, preventative and predictive maintenance, qualification, personnel training, and performance monitoring. The role collaborates with process engineering and R&D to develop robust equipment and processes, apply statistical validation, and execute improvement projects supporting high-volume manufacturing.

Performs end-to-end physical IC design from RTL through silicon tape-out, including synthesis, physical verification, timing closure, EM/IR analysis, place and route, clock tree synthesis, floorplanning, layout, and methodology development. Collaborates with RTL engineers and develops physical design flows using TCL/Perl scripting and EDA tools. The role is fully onsite and supports PCIe switch and enterprise storage products.

Performs full physical IC design from RTL through silicon tape-out, including synthesis, physical verification, timing closure, EM/IR analysis, place and route, clock tree synthesis, floorplanning, layout, and methodology development. Collaborates with RTL engineers and requires expertise in EDA tools, TCL/Perl scripting, top-level static timing analysis, and in-person execution in Colorado Springs.

Designs and implements high-performance digital IC RTL for PCIe switch and enterprise storage products. Responsibilities include architecture analysis, micro-architecture development, Verilog/SystemVerilog implementation, clock-domain crossing, low-power design, timing closure, RTL debugging, third-party IP integration, cross-functional collaboration, and silicon validation support. The role is fully onsite and requires extensive industry experience in digital IC design.

Performs end-to-end physical IC design from RTL through silicon tape-out, including synthesis, physical verification, timing closure, EM/IR analysis, place and route, clock tree synthesis, floorplanning, layout, and methodology development. Collaborates with RTL design engineers and works onsite. Requires TCL/Perl scripting, EDA tool proficiency, a bachelor’s degree in electrical or electronics engineering, and 12+ years of relevant experience.

Execute the full physical design cycle from RTL through silicon tape-out, including synthesis, physical verification, timing closure, EM/IR analysis, place and route, clock tree synthesis, floorplanning, layout, and methodology development. Collaborate with RTL design engineers and develop scripting-based flows. The role requires in-person work, a bachelor's degree in electrical or electronics engineering, and 12+ years of relevant experience.

Lead project management for 20+ concurrent ASIC package design projects involving complex flip-chip BGA packages, high-speed SerDes, HBM, DDR5, and high-power delivery. Create schedules, coordinate global engineering teams, customers, vendors, and cross-functional partners, track risks, improve methodologies, and communicate project status. Contribute to package design rules, technical methodologies, design-for-X tradeoffs, SI/PI, thermal and mechanical modeling, automation, and new business quotes.

Provides senior-level technical consulting for mainframe infrastructure environments and Broadcom Software products. Responsibilities include solution architecture, product implementation and upgrades, integrations, demonstrations, proofs of concept, troubleshooting, technical documentation, customer presentations, and post-implementation support. The consultant advises clients and management on infrastructure strategies and works with account teams to design solutions. Requires expertise in z/OS, Broadcom mainframe tools, REXX or HLASM, and major mainframe subsystems and security managers. Client-site travel is required.

Develop, test, maintain, and optimize firmware and software for high-speed serial communication and data conversion IPs. Refactor legacy systems, build regression tests, support Jenkins CI/CD pipelines, administer Linux compute clusters, and debug hardware-software interactions using lab equipment and RTL simulations. The role also involves field issue resolution, documentation, cross-functional collaboration, and mentoring.

Develops advanced 2.5D and 3D ASIC package solutions, balancing signal integrity, thermal performance, structural reliability, cost, and manufacturing requirements. Leads package technology development, qualification, supplier and customer engagement, sourcing, NPI, and production ramps. Collaborates with silicon, package design, test, marketing, and assembly teams while applying thermal and mechanical modeling and CAD tools to optimize substrates, interposers, materials, and assembly processes.

Develop and support software tools, methodologies, and automated flows for ASIC design and implementation. Responsibilities include scripting and C++ development, debugging design tools and flows, supporting IC designers, collaborating with EDA vendors, training global engineering teams, and documenting internal tools. The role requires digital logic and Verilog knowledge, software development expertise, static timing analysis, and power delivery verification experience.

Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G applications. Responsibilities include package layout, signal and power integrity, thermal and reliability considerations, manufacturability, and design of SerDes, ADC/DAC, DDR, and related structures. The engineer manages multiple projects, collaborates with global teams and vendors, interfaces with customers, and improves design processes through automation and documentation. This is a fully onsite role.

Design Engineer on Broadcom's Custom Silicon Design Team working on physical implementation of high-performance ASICs (3 nm and below). Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and signoff. Work in UNIX environments, use TCL (Python/Perl preferred) and commercial/in-house EDA tools, collaborate cross-functionally, and contribute to design flow automation and silicon bring-up. Requires Electrical/Electronics Engineering degree and strong VLSI/ASIC fundamentals.

Develops chip-level timing architecture, constraints, analysis, and signoff for advanced ASIC and SoC designs. Responsibilities include MMMC STA, pre- and post-route analysis, timing ECOs, violation debugging, signal integrity and clock analysis, timing-flow automation, and power/performance optimization. Collaborates with physical design, synthesis, and clock teams while contributing technical leadership, mentoring, methodology improvements, and timing documentation.

Executes the full physical IC design cycle from RTL through silicon tape-out, including synthesis, physical verification, timing closure, EM/IR analysis, place and route, clock tree synthesis, floorplanning, layout, and methodology development. Collaborates with RTL design engineers and applies TCL/Perl scripting and EDA tools. This is an in-person role in Colorado Springs, Colorado.

Lead DFT programs including specification, implementation, and verification for ASIC products, focusing on various phases of SoC DFT-related activities and customer interactions.

Designs complex front-end RTL IP blocks for leading-edge Ethernet switching silicon used in AI/ML and cloud data centers. Responsibilities include collaborating with global architecture and design teams, developing new device products, and emphasizing design and silicon debug. The role requires strong communication, documentation, self-direction, and teamwork, along with extensive industry experience in RTL design and familiarity with Python or Perl.

Architect, design, implement, and maintain low-level firmware, middleware, and diagnostic software for PHY chipsets. Develop and troubleshoot embedded C/C++ applications, collaborate with system and hardware designers, and provide leadership in architecture, design patterns, and code quality. Support the full development lifecycle, including pre-silicon co-simulation, laboratory hardware platforms, and silicon bring-up.

Designs and supports semiconductor timing solutions using static timing analysis, physical design principles, timing constraints, signal integrity, clock networks, and timing models. Debugs timing-tool errors, generates reports, analyzes setup and hold timing, and works with large datasets. Collaborates independently with geographically distributed engineering teams, manages multiple assignments, communicates findings clearly, and may supervise others. Requires extensive electrical or computer engineering experience and TCL programming.