Jobs at Intel

Lead architecture strategy for multi-die chiplet SoC platforms: define chiplet partitioning, D2D interconnect and QoS, power/clock/boot infrastructure, RAS/debug/telemetry, and system-level PPA/cost/yield trade studies. Drive cross-functional alignment and produce executive architecture recommendations for scalable data-center networking SoCs.

Lead design, simulation, layout collaboration, and verification of analog and mixed-signal ICs (PLLs, data converters, TX/RX, power delivery) for high-speed IO and die-to-die interfaces. Drive projects from specification to silicon, mentor junior engineers, coordinate global cross-functional teams, develop test plans, perform post-silicon validation and optimization for performance, power, and area.