Search the 2 jobs at Hudson River Trading

The FPGA/ASIC Verification Engineer will be responsible for creating testbenches, writing detailed verification plans, collaborating with designers, managing regression and continuous integration infrastructure, and developing open-source and internal tools. The ideal candidate should have strong analytical skills, experience in RTL functional verification, and familiarity with Linux and Python. C++ experience and knowledge of networking protocols are preferred. A bachelor's degree in Computer or Electrical Engineering is required. This is a full-time position with a minimum base salary of $150,000.

Responsible for building and maintaining tools and software features to automate systems engineering workflows. Troubleshoot software bugs on Linux machines. Build and maintain CI/CD pipelines for code testing and deployment. Write configuration management code. Set the direction for the Systems Python platform.