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The Design Verification Engineer will create testbenches, develop verification plans, and manage test suites for FPGA and ASIC hardware platforms. Responsibilities include debugging RTL bugs, collaborating with designers, and enhancing tools in a fast-paced trading environment.

As a Senior Systems Software Engineer, you will develop tools to enhance the configuration management system and improve the development experience. Your responsibilities include building and maintaining automation tools, troubleshooting software issues on Linux systems, and integrating configuration management modules.

The FPGA/ASIC Verification Engineer at Hudson River Trading will develop testbenches, verify complex hardware designs, and improve tools in a fast-paced trading environment. Collaboration with designers and management of continuous integration processes are key aspects of this role. Strong analytical skills and a solid background in RTL verification are required.