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Systems Engineer role at Hudson River Trading involving projects to improve Linux research systems, manage distributed compute clusters, automate technical infrastructure, troubleshoot hardware/software issues, and optimize performance.

Seeking an experienced FPGA Verification Engineer to create testbenches and build verification environments for complex hardware. Responsible for writing detailed verification plans, debugging RTL bugs, and collaborating with designers. Must have strong debugging and analytical skills, 4+ years of experience in RTL functional verification for FPGA or ASIC, experience with code and functional coverage collection/analysis, and proficiency in Python and Linux. Knowledge of Verilator and/or Cocotb preferred. Networking protocol experience is a plus. Bachelor's degree in Computer or Electrical Engineering or related field required.

The FPGA/ASIC Verification Engineer will be responsible for creating testbenches, writing detailed verification plans, collaborating with designers, managing regression and continuous integration infrastructure, and developing open-source and internal tools. The ideal candidate should have strong analytical skills, experience in RTL functional verification, and familiarity with Linux and Python. C++ experience and knowledge of networking protocols are preferred. A bachelor's degree in Computer or Electrical Engineering is required. This is a full-time position with a minimum base salary of $150,000.

Responsible for building and maintaining tools and software features to automate systems engineering workflows. Troubleshoot software bugs on Linux machines. Build and maintain CI/CD pipelines for code testing and deployment. Write configuration management code. Set the direction for the Systems Python platform.